Verikwest is pleased to offer a two-day workshop "Introduction to SystemVerilog" that cover the basics of the SystemVerilog Language. The course will provide an introduction to all the SV constructs that are used by verification engineers.
Anyone interested in learning the basics (or refreshing their knowledge) of the SV language
As chip complexities increase, improving the efficiency of design verification has become an important requirement for all semiconductor companies. Design teams are constantly challenged to improve their verification and integration methodologies. VeriKwest Systems Inc was founded in 2011, with the main vision of helping customers build custom CAD solutions focused on SOC integration and Verification.
The VeriKwest team has in-depth experience in 3 major areas of design and verification for semiconductors.