Design and Verification Training

VeriKwest has 6 years of experience providing highly customized onsite design and verification training for top semiconductor companies. We customize each course to make sure that your engineers are trained

  • on your design and verification languages (SystemVerilog, Verilog or VHDL)
  • based on your coding guidelines
  • and your design and verification methodologies

Many engineers have benefitted from our customized courses in the following areas:

  • SystemVerilog Basics
  • SystemVerilog Testbench including OOP techniques
  • SystemVerilog Assertions
  • SystemVerilog for designers
  • OVM
  • UVM
  • Advanced UVM Concepts
  • UVM Reg

For more information about our design and verification training, please contact us info@verikwest.com