Senior Verification Engineer

Job Description: 

We are currently engaged in several verification projects with large semiconductor houses. We are looking for senior Verification Engineers for our clients in Bangalore. As a senior verification engineer, you will be responsible for:

  • Creation of verification plans
  • Implementation of testbench environments in OVM/UVM
  • Understanding how to use commercially available VIPs necessary for the protocols used in the design
  • Implementation of sequences and virtual sequences
  • Configuring uvm_config_db database correctly (for each test)
  • Creation of multiple tests based on the verification plan
  • Implementation of the scoreboard
  • Definition and implementation of the functional and code coverage plans
  • Definition and implementation of the assertion plan
  • Migration of the verification environment to SOC level
Educational Qualfications: 
Masters or Bachelors degree in Computer Science/ Computer Engineering or Electronics Engineering
Required Experience: 
2 to 5 years experience in block level or SOC level verification
Job Location: 
Bangalore, India
Required skills: 

In order to be successful the right candidate is expected to have:

  • At least 2 years of verification experience dealing with complex blocks or SOCs
  • Proven expertise in OVM or UVM
  • Experience with at least one of the leading simulators in the industry
  • Ability to debug SystemVerilog code using state-of-the-art debugging techniques
  • Knowledge of common protocols such as (PCIE, AXI, USB)
  • Previous experience with commercial Verification IPs (VIPs)