RTL design engineer
Job Description:
We are looking for engineers with RTL design expertise to help support our clients areas of RTL to GDSII flow
- Synthesis
- Static Timing Analysis
- Signal Integrity
- Timing correlation
- Clock Domain Crossing
- Design rule checks
Educational Qualfications:
Masters or Bachelors degree in Computer Science/ Computer Engineering. or Electronics Engineering
Required Experience:
3 to 5 years experience in ASIC design
Job Location:
Bangalore, India
Required skills:
- 3-5 yrs experience in RTL design with Verilog
- Must have atleast 2 years of work experience in working on one of the following technologies
- Gate Level Synthesis,
- State Timing Analysis
- Signal Integrity,
- Timing correlation,
- Clock Domain Crossing
- Design rule Checks
- Low power checks
- . Should have used industry standard tools like Design Compiler, Prime Time, Conformal, Spyglass
- Good communication and leadership skills to interface with customer
- Enthusiasm and self-motivation to learn new technologies