Verification of a RISC-V based SOC
RISC-V is an open instruction set architecture (ISA) developed at the University of California, Berkeley.. The RISC-V ISA has been designed with small, fast, and low-power real-world implementations in mind, Hence it will be useful for modern devices such as cloud computers, high-end mobile phones and the smallest embedded systems. Such uses demand that the designers consider both performance and power efficiency. The instruction set also has a substantial body of supporting software, including the entire tool chain to successfully compile and run complex code on the ISA.
There are several companies adopting (or planning to adopt) RISC-V architecture for their next SOC design. In this project we have implemented a complete verification framework for a RISC-V based SOC. This framework is designed in UVM and incorporates the following UVM based VIPs.
We have developed several tests to exercise the entire SOC. Each test contains two parts
- a "C"-based component which provides the instructions for the CPU to execute
- an UVM-based component which provides external stimuli through the VIPs and provides overall control of the test
For more information about this project, or if you are interested any SOC verification services, please contact us email@example.com